The present application claims the benefit of Korean Patent Application No. 87285/2000 filed Dec. 30, 2000, under 35 U.S.C. xc2xa7119, which is herein fully incorporated by reference.
1. Field of the Invention
The present invention relates to a micro-controller unit, and more particularly, to a power noise prevention circuit in a micro-controller unit (MCU).
2. Discussion of the Related Art
FIG. 1 shows a power noise prevention circuit in an MCU according to a first embodiment as disclosed in U.S. Pat. No. 6,097,226, which is owned by the same assignee of the present invention.
Referring to FIG. 1, in the power noise prevention circuit, a power fail detection circuit 10 and a reset circuit 11 are provided. When a power is reduced to a level insufficient for operating the MCU normally due to a power noise inputted to the MCU, the power fail detection circuit 10 detects the power failure and generates a power fail signal. The reset circuit 11 receives the power fail signal and prevents the MCU from being operated falsely in accordance with the power noise by resetting the MCU.
FIG. 2 shows a power noise prevention circuit in an MCU according to a second embodiment as discussed in the above-discussed U.S. Pat. No. 6,097,226.
Referring to FIG. 2, in this power noise prevention circuit, a power fail detection circuit 22, a system clock generating circuit 20, and a clock freezing and synchronizing circuit 21 are provided. When the power is at a normal level, the system clock generating circuit 20 produces a system clock signal SCLK1 by receiving a basic clock signal ICLK from an oscillator. The clock freezing and synchronizing circuit 21 is synchronized by the system clock signal SCLK1 and outputs another system clock signal SCLK2, which is identical to the system clock signal SCLK1, to an internal circuit.
The power fail detection circuit 22 enables a power fail signal POWER FAIL if a power noise is inputted to the MCU. The clock freezing and synchronizing circuit 21 outputs the system clock signal SCLK2, which is transferred to the internal circuit, as a fixed state of the system clock signal SCLK1 at the moment of the power-failure in accordance with the enabled power fail signal. As a result, the internal state of the MCU is temporarily frozen during the power-failure.
If the power fail signal is disabled as the power is restored normally, the clock freezing and synchronizing circuit 21 is synchronized again by the system clock signal SCLK1 and outputs a system clock signal SCLK2 identical to the system clock signal SCLK1 to the internal circuit. Therefore, the MCU is able to carry out the next operation normally.
As mentioned in the above explanation, the power noise prevention circuit according to the first embodiment of the related art always resets the MCU if a power noise is inputted thereto. Unfortunately, if the MCU is always reset responsive to the power noise input, the entire system itself equipped with the MCU becomes initialized. For instance, a TV set which is turned on becomes turned off, a wash machine stops (even during a washing operation) and returns to the initial state, or a medical appliance which is being used will stop operating suddenly. Such events are inconvenient to users and can have serious consequences.
Moreover, the power noise prevention circuit according to the second embodiment of the related art freezes the internal state of the MCU temporarily by holding the system clock signal temporarily when a power noise is inputted thereto. Then, after the power has been restored, the power noise prevention circuit is able to carry out a successive operation by releasing the frozen internal state of the MCU.
But, if the power is reduced to a level at which a CMOS of the MCU is unable to operate normally, the frozen MCU may enter a state unwanted or unpredicted by the user. To avoid this problem, a general MCU may include a reset circuit to reset the MCU when the power is reduced to the level at which the CMOS is unable to operate normally. However, these levels differ depending on different products and applications, which is generally not recognized and understood by users.
Accordingly, the present invention is directed to a power noise protection circuit in a micro-controller unit that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a power noise protection circuit in a micro-controller unit that effectively prevents the abnormal operation of the MCU due to a power noise.
Another object of the present invention is to provide a power noise protection circuit in a micro-controller unit that allows a user to adjust properly a power fail detection method in accordance with the application.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a power noise protection circuit in a micro-controller unit according to an embodiment of the present invention includes a system clock producing circuit producing a system clock signal by receiving a clock signal, a clock-freeze and synchronization part outputting fixedly the system clock signal outputted from the system clock producing circuit during power failure, a reset circuit resetting an MCU during the power failure, a power fail detection circuit dividing a detection level of a power into a freeze level and a reset level, the power fail detection circuit operating the clock-freeze and synchronization part when a power level reaches the freeze level, and the power fail detection circuit operating the reset circuit when the power level reaches the reset level, and a power fail detection register controlling a detection operation and a detection mode of the power fail detection circuit.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.